Higher performance, lower cost, increased miniaturization of semiconductor components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. One way to reduce the overall cost of a semiconductor component is to reduce the manufacturing cost of that component. Lower manufacturing costs can be achieved through faster production as well as in reduction in the amount of materials used in fabricating the semiconductor component. In recent years, the semiconductor industry has greatly expanded its emphasis in development and production of electro-optical components, such as, for example, charge-coupled devices (CCDs) and, more recently, CMOS imagers. As with other semiconductor components, there is a continued drive toward higher performance parameters and greater yields at ever-lower costs.
Micro-electromechanical systems (“MEMS”) is another technology receiving a great deal of attention in many industries, including the electronics industry. MEMS integrate microminiature electrical and mechanical components on the same substrate, for example, a silicon substrate, using microfabrication technologies to form extremely small apparatuses. The electrical components may be fabricated using integrated circuit fabrication (“IC”) processes, while the mechanical components may be fabricated using micromachining processes that are compatible with the integrated circuit fabrication processes. This combination of approaches makes it possible, in many instances, to fabricate an entire microminiature system on a chip using conventional manufacturing processes. However, there remain many shortcomings in existing fabrication technologies that limit the types and sizes of MEMS components and assemblies, which may be fabricated.
Conventional IC processing for DRAM, microprocessors, etc., are currently performed on (100) silicon. Potassium hydroxide and TMAH may be used to create vertical etches in (110) silicon by using (110) substrate wafers or causing the recrystallization of the surface of a substrate wafer to have a (110) crystal orientation. However, the resultant structures are not always desirable and may introduce costly, additional processing steps and procedures to the fabrication process and create a low performance device.
Various conventional chemistries have been used to etch silicon. For example, both single crystal and polycrystalline silicon are typically wet etched in mixtures of nitric acid (HNO3) and hydrofluoric acid (HF). With use of such etchants, the etching is generally isotropic. The reaction is initiated by the HNO3, which forms a layer of silicon dioxide on the silicon, and the HF dissolves the silicon oxide away. In some cases, water is used to dilute the etchant, with acetic acid (CH3COOH) being a preferred buffering agent.
In some applications, it is useful to etch silicon more rapidly along one or more crystal planes relative to others. For example, in the diamond lattice of silicon, generally the (111) plane is more densely packed than the (100) plane, and thus the etch rates of (111) orientated surfaces are expected to be lower than those with (100) orientations. Bonding orientation of the different planes also contributes to etchant selectivity to exposed planes. One etchant that exhibits such orientation-dependent etching properties consists of a mixture of KOH and isopropyl alcohol. For example, such a mixture may etch about one hundred (100) times faster along (100) planes than along (111) planes.
Hydroxide etchants and TMAH may be used to create a vertical undercut in (100) silicon. FIGS. 1A-2B show a silicon etch performed with different etchant solutions in both the standard silicon orientation (FIG. 1A and FIG. 2A) and 45° rotation (FIG. 1B and FIG. 2B). In the standard orientation, a mask is aligned along the <110> directions. The {111} planes define the sidewalls which are sloped from (100) surface plane. With the 45° rotation, the mask is aligned along the <100> direction. In FIG. 1, the etchant was dilute NH4OH applied at 26° C. and in FIGS. 2A and 2B, the etchant was dilute TMAH applied at 26° C. While the two etchants display different selectivity, both undercut the silicon 10 and create beveled edges or chamfers 12. The beveled edges may be undesirable for some applications and may limit the spacing of components on the integrated circuit.
Accordingly, it would be desirable to create square undercuts in (100) silicon without beveled edges, or chamfers and/or to manipulate the shape of the undercut. Further, it would be desirable to create a lateral shelf in (100) silicon using wet etch chemistry.